High density integration of high-mobility channel materials for CMOS technology is an enormous challenge for the semiconductor industry. Typically, SRAM arrays are the most dense pattern on a CPU layout. Therefore, it is the most critical circuit for any advanced CMOS technology featuring heterogeneous integration of high mobility channel materials. Materials such as InGaAs nFETs and SiGe pFETs are among the leading candidates for sub-10 nm nodes. Currently, the industry preferred approach to integrate InGaAs on Si relies on selective epitaxy in SiO2 cavities.
In order to deal with the challenges involved in such circuitry, Design/Technology co-optimization has become a strategic field for CMOS manufacturers. This means that device technology and circuit design cannot anymore be treated as two separate entities. Strong requirements may exist on the technology side which strongly impact the design and vice-versa. Introducing InGaAs by selective epitaxy in SiO2 cavities into CMOS manufacturing will add another level of complexity on the technology side. This increased complexity has to be accounted for on the circuit design side.
Accordingly, a need arises for techniques by which SRAM cells may be designed that are compatible with the requirements of InGaAs integration by selective epitaxy in SiO2 cavities without sacrificing density and area scaling.